`timescale 1ns / 1ps
module fenpinqi(CLK_IN,CLK_OUT);
    input CLK_IN;
    output CLK_OUT;
    reg A = 0;
    reg [31:0] counter = 0;
    parameter R = 1;
    always@(posedge CLK_IN)
        begin
            if (counter==R-1)
                begin
                    counter <= 0;
                    A <= ~A;
                end
            else
                counter <= counter + 1;
        end
    assign CLK_OUT = A;
endmodule
